Data buses are found in electronic devices such as computer printed circuit boards, integrated circuit devices, personal digital assistants, cellular telephones, and most other electronic devices. A data bus can be a collection of lines that are primarily used to transmit data from one location to another.
Data is represented on a data bus in the form of binary digits, also known as bits. Each bit in turn represents only one of two values, a “0” (also referred to as an “off”), or a “1” (also referred to as an “on”). These two values are physically represented on the data bus in the form of electrical signals. A low voltage signal, ideally at zero volts, corresponds to the “0”, while a high voltage signal, ideally at the power supply voltage (e.g., 1.8v or 3.3v), corresponds to the “1”. In this description, these low voltage and high voltage signals are also referred to simply as “low signals” and “high signals.”
In an integrated circuit (IC) device, a data bus can couple a plurality of devices, such as data banks or memory banks, to a plurality of input/output (I/O) buffers. As used herein, the terms “coupled,” “connected,” or any variant thereof, means any connection or coupling, either direct or indirect, between two or more elements. These I/O buffers may, in turn, be coupled to leads that can carry the data outside the integrated circuit device. So when data needs to be transmitted from a data bank of an IC device to any other part of a computer, the data normally travels out of the data bank through a bit line, across the data bus, and then out an I/O buffer. And when data needs to be transmitted into a data bank on the IC device, the data comes in through an I/O buffer, travels across the data bus, and then goes into the data bank though a bit line.
FIG. 1 illustrates an integrated circuit device 10 having a data bus architecture 12 implemented according to previously developed techniques. Here, an eight-bit data bus 14 (i.e., composed of eight lines) is formed on a semiconductor die 16. Data bus 14 connects four data banks 18 to I/O buffers 20. Data banks 18 represent any devices or components that can be used in conjunction with a data bus, including but not limited to memory banks (e.g., RAM, DRAM, or ROM) or processing blocks. Each data bank 18 in this architecture 12 is coupled to data bus 14 through bit lines 22, multiplexers 24, and bit lines 26. Each multiplexer 24 is used to multiplex two bit lines 22 down to one bit line 26.
A number of tri-state buffers (not expressly shown) may be used to provide the energy required to drive data signals along bit lines 22 and 24 to I/O buffers 20 across data bus 14. In particular, tri-state buffers drive high data signals from data banks 18 to I/O buffers 20 by providing current to charge data bus 14 up to a high voltage level.
In the previously developed data bus architecture 12, the data bus 14 spans almost the entire side of the semiconductor die 16 on which it is implemented. The length of the data bus 14 gives rise to a significant amount of electrical resistance and/or parasitic or other capacitance. As such, a significant amount of time may be required for the driving tri-state buffers to charge the whole data bus 14 from around zero volts (which is the starting voltage level for data bus 101) up to a voltage level that can be sensed or detected as a high signal by an I/O buffer 20. The greater the length of the data bus 14, the more time is required to charge it to a high level due to increased levels of resistance and capacitance from the increased wire length. All of this time acts to lower the response time of data bus 14, resulting in slower system performance.
The use of a tri-state scheme to drive data signals from data banks to I/O buffers on long data bus lines therefore suffers from limitations. The loading is larger on a tri-state buffer, and a significant amount of time may be required for a tri-state buffer to charge the entire length of the data bus. Accordingly, there is a need for a faster and more dynamic way to drive data signals from data banks to I/O buffers.
The disadvantages and problems associated with driving data signals in previously developed bus architectures, particularly through the use of tri-state buffers, has been substantially reduced or eliminated using the present invention.
According to one embodiment of the present invention, a system is provided for driving data signals in an integrated circuit device. The system includes a plurality of functional blocks, each having at least one input/output connection along one side of the integrated circuit device. A data bus comprises a plurality of electrically independent segments. Each segment of the data bus spans a respective portion of the one side of the integrated circuit device. A plurality of lines electrically couple the input/output connections of the functional blocks to the segments of the data bus. The lines are grouped into a plurality of subsets, and each subset is electrically coupled to a different segment of the data bus.
According to another embodiment of the present invention, a system is provided for driving data signals in an integrated circuit device. The system includes a data bus comprising two or more electrically independent segments. Each segment extends along less than half a length of a side of the integrated circuit device. A data bank has a set of input/output connections. The set of input/output connections comprises two or more subsets, each of the subsets electrically coupled to a different data bus segment.
Important technical advantages of the present invention are readily apparent to one skilled in the art from the following figures, descriptions, and claims.